鈥?/div>
Single Chip L2 Cache for PowerPC
66 MHz Zero Wait State Performance (2鈥?鈥?鈥? Burst)
Four鈥揥ay Set Associative Cache Design
32K x 72 Data Memory Array
8K x 18 Tag Array
Address Parity Support
LRU Cache Control Logic
Copy鈥揃ack or Write鈥揟hrough Modes of Operation
Copy鈥揃ack Buffer for Improved Performance
Single 3.3 V Power Supply
5 V Tolerant I/O
One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB)
Single Clock Operation
Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)
Supports up to Four Processors in a Shared Cache Configuration
High Board Density 25 mm 241 PBGA Package
BLOCK DIAGRAM
ZP PACKAGE
PBGA
CASE 1138鈥?1
COPY鈥揃ACK
BUFFER
CONTROL
RD/WR
60X BUS
INTERFACE
A27, A28
CONTROLLER
AND
BUS INTERFACE
RD/WR
2K x 18 x 4
TAG RAM
2K x 8 LRU
8K x 72 x 4
DATA RAM
DH0 鈥?DH31
DL0 鈥?DL31
DP0 鈥?DP7
WAY SELECT
A0 鈥?A31
COMPARE
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 6
2/26/98
漏
Motorola, Inc. 1998
MOTOROLA
MPC2605
1