For Communications Equipment
MN86063
High-Speed CODEC LSI for Facsimile Images
Overview
The MN86063 is a high-speed LSI codec for compressing
and decompressing facsimile images. Features include
real-time printing to laser printers, built-in line memory,
enlargement and reduction, and code conversion.
Function
Message coding:
MH, MR, MMR, and MG3. The chip also supports
data transfers on the image and system buses and DMA
transfers on the image bus alone.
Coding conversion
The chip converts between all supported message
coding systems: MH, MR, MMR, and MG3.
Enlargement/reduction
These may be added to coding, decoding, code
conversion, and data transfer operations.
(1) In the primary scan direction, the chip uses
multiplication on the change point address. The
scaling factor can be anywhere between approximately
0.1% and 200% in increments of approximately
0.1%. Integral multiplication is also available
beyond this
(2) In the subscanning direction, the chip uses
decimation and replication. The scaling factor can
be anywhere between approximately 0.0015% and
200% in increments of approximately 0.0015%.
Integral multiplication is also available from 2 to
65,535.
White masks for both edges
These may be added to coding, decoding, code
conversion, and data transfer operations. They change
all pixels within the margins, specified in bit
increments, to white.
Decoding error processing
The chip offers a choice of replacing with the previous
line or a white line.
Features
Pixels per line:
between 16 and 4864 bits, in word (16-bit) increments.
Processing time per line:
Individual pixels are processed within two system
clock cycles. For a machine cycle of 10 MHz,
processing the worst-case pattern for a 4096-bit line
takes no more than 1 ms.
Time-shared, multiplex processing
Support for time-shared, multiplex processing allows
image I/O, enlargement/reduction processing, and
coding/decoding to proceed concurrently for a group
of lines. Image bus DMA transfers can also proceed
concurrently with command processing.
Multiple channels
If lines consist of 2432 bits or fewer, commands can
be processed simultaneously on two channels using
time-sharing. These commands may be issued
asynchronously.
Bus configuration
There are separate system and image buses. The latter
features two independent master DMA channels; the
former, four slave DMA channel pins.
Image data I/O
Image data I/O can use either the image or system bus.
Byte conversion
When the system bus is 16 bits wide, the chip can swap
the upper and lower bytes of image or coded data. It
can also swap the MSB and LSB.
Memory management
The chip includes pointer management for the image
buffer connected to the image bus.
Machine cycle
The limit is 10 MHz. This means that the maximum
input clock is twice this, or 20 MHz.
Applications
Facsimile equipment
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