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MN6155 Datasheet

  • MN6155

  • PLL LSI with Built-In Prescaler

  • 56.36KB

  • 9頁

  • PANASONIC

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For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data parameter
input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (1.65
mW for V
DD
=1.1 V, F
IN
= R
IN
=90 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
It also offers two choices for the reference signal: self-
excited operation using the built-in inverter amplifier or
use of an external, separately excited oscillator.
Pin Assignment
X
IN
X
OUT
FV
V
DD
D
OP
V
SS
V
CP
F
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
IN
RSL
LC
FR
PS
LE
DATA
CLK
(TOP VIEW)
SSOP016-P-0225
Features
Low power supply voltage: V
DD
=1.0 to 1.4V
Low power consumption: 1.65mW(V
DD
=1.10V,
F
IN
=90MHz, R
IN
=90MHz)
High-speed operation: F
IN
=90MHz, R
IN
=90MHz
(V
DD
=1.1V)
Frequency dividing ratios in reference frequency
dividing stage
6 to 131,070 for RSL at "H" level
(even number setting is available)
272 to 131,071 for RSL at "L" level
Frequency dividing ratios for comparator stage: 272
to 262,143
Power supply pin for built-in charge pump
V
CP
=2.5 to 3.2V
Output monitor pins for both comparator and reference
frequency dividing stages

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