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MN3307 Datasheet

  • MN3307

  • Panasonic Semiconductor [1024-Stage Ultra Low Voltage Opera...

  • 61.07KB

  • PANASONIC

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MN3300 Series
MN3307
1024-Stage Ultra Low Voltage Operation BBD for Audio Signals
s
Overview
The MN3307 is a 1024-stage ultra low voltage operation BBD
variable delay line in audio frequency range. The device operates on
+3
V supply and provides a signal delay up to 51.2 ms and is suitable
for use as reverberation effect of low voltage operation audio equip-
ment such as portable stereo, radio cassette recorder and microphone.
GND
1
2
MN3307
IN
V
DD
3
4
6
5
CP1
V
D1
8
7
V
D2
OUT
s
Pin Assignment
s
Features
鈥?/div>
Variable signal delay of the audio signal : 1.024 to 51.2 ms
鈥?/div>
Wide range of supply voltage : 1.8 to 5.0 V
鈥?/div>
No insertion loss : L
i
=0
dB typ.
鈥?/div>
Wide dynamic range : S/N=69 dB typ.
鈥?/div>
Low distortion : THD=0.6 % typ. (V
i
=0.22
V
rms
)
鈥?/div>
Clock frequency range : 10 to 200 kHz (1.8 V鈮
DD
<4.0
V)
10 to 500 kHz (4.0 V鈮
DD
鈮?.0
V)
鈥?/div>
N-channel 2-layer silicon gate process
鈥?/div>
8-Pin Dual-In-Line Plastic Package
CP2
DIP008-P-0300
CP1
6
鈥?/div>
Reverberation and echo effects of audio equipment such as radio
cassette recorder, car radio, portable radio, portable stereo, echo
microphone and Karaoke machine, etc.
鈥?/div>
Sound effect of electronic musical instruments
鈥?/div>
Variable or fixed delay of analog signals
2
CP2
s
Applications
s
Block Diagram
8
7
5
V
D2
OUT
V
D1
IN
3
1024-Stage
BBD
4
s
Pin Descriptions
Pin No. Symbol
1
2
3
4
GND
CP2
IN
V
DD
Pin Name
Ground pin
Clock input 2
Signal input pin
V
DD
apply pin
Connected to ground.
Basic clock pulse is applied to transfer electric charge of BBD.
Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse
input gate of the BBD transfer gate.
Furthermore, voltage is supplied to step-up circuit.
The same phase clock pulse as CP1 is applied through capacitor.
Clock pulse of inverted phase to CP2 is applied.
Composed signal of 1024th and 1025th stages is output.
The same phase clock pulse as CP2 is applied through capacitor.
Description
5
6
7
8
V
D1
CP1
OUT
V
D2
V
D1
apply pin
Clock input 1
Output pin
V
D2
apply pin
GND
V
DD
1
1

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