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MN195001 Datasheet

  • MN195001

  • Single-Chip Fax Engine LSI

  • 6頁

  • PANASONIC

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For Communications Equipment
MN195001
Single-Chip Fax Engine LSI
Overview
The MN195001 reduces to a single chip CPU functions
related to facsimile control, peripheral device control
functions, and modem functions. The last include
complete fax/modem support for the ITU-T G3
recommandations V.29, V.27ter, and V.21 Channels 1
and 2.
The MN195001 consists of the following blocks: digital
signal processor (DSP), facsimile peripheral circuits,
analog circuits, DTE interface, clock generator, and dual-
port RAM. Changing the contents of an external ROM
tailors the chip for a wide variety of facsimile applications.
Features
Digital signal processor (DSP) block
鈥?Micro ROM: 4096
脳
32 bits
鈥?Data RAM: 512
脳
16 bits
脳
2 sets
鈥?Machine cycle: 90 ns
鈥?Parallel multiplier:
16 bits
脳
16 bits
脳 鈫?/div>
32 bits
鈥?Arithmetic and logic unit (ALU): 32-bit
Facsimile peripheral circuit block
鈥?Scanner/plotter interface
鈥?Two USART channels
鈥?Two motor control channels
鈥?One thermal head control channel
鈥?Programmable chip select
Analog circuit block
鈥?Built-in 8-bit D/A converter, A/D converter, and
filters
DTE interface block
鈥?Built-in 8-bit I/O interface and serial interface
Clock generator block
鈥?Sampling clock and baud rate clock generators
Dual-port RAM block
鈥?1024
脳
8 bits
Single 5 volt power supply
Applications
Facsimile equipment

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