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MN101EF30R Datasheet

  • MN101EF30R

  • MN101E30R

  • 390.33KB

  • 3頁

  • PANASONIC

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MN101E30R
Type
Internal ROM type
ROM (byte)
RAM (byte)
Package (Lead-free)
Minimum Instruction
Execution Time
MN101E30R
Mask ROM
928K
6K
QFP100-P-1818B (Under development)
50
ns (at
2.2
V to
5.5
V,
20
MHz)
50
ns (at
2.2
V to
5.5
V,
20
MHz)
* at internal
2
,
3
,
4
,
5
,
6
,
8
,
10
times oscillation used
MN101EF30R
FLASH
飩?/div>
Interrupts
6
external interrupts,
30
internal interrupts
RESET, Watchdog, External
0
to
4,
Timer
0
to
4,
Timer
6,
Timer
7
(2 systems), Timer
8
(2 systems), Timer
9
(2 systems), Time
base, Serial
0
(2 systems), Serial1 (2 systems), Serial
2
(2 systems), Serial
3
(2 systems), Serial
4,
Serial
5,
A/
錛?/div>
conversion 鏗乶ish,
Automatic transfer (2 systems), Key interrupts, end of single tone, end of phrase
Timer counter
0
:
8-bit
脳
1
(timer pulse output, event count, added pulse (2-bit) system PWM output, generation of remote control carrier, simple
pulse measurement, real time output control)
Timer counter
1
:
8-bit
脳
1
(timer pulse output, event count,
16-bit
cascade connected (timer
0, 1)
timer synchronous output event)
Timer counter
2
:
8-bit
脳
1
(timer pulse output, event count, added pulse (2-bit) system PWM output, simple pulse measurement,
24-bit
cascade
connected (timer
0, 1, 2),
timer synchronous output event, real timer output control)
Timer counter
3
:
8-bit
脳
1
(timer pulse output, event count, generation of remote control carrier,
16-bit
cascade connected (timer
2, 3), 32-bit
cascade connected (timer
0, 1, 2, 3))
Timer counter
4
:
8-bit
脳
1
(timer pulse output, added pulse (2-bit) system PWM output, event count, serial transfer clock, simple pulse measurement)
Timer counter
6
:
8-bit
free run timer, time base timer
飩?/div>
Timer Counter
Timer counter
7
:
16-bit
脳
1
(timer pulse output, event count, High accuracy PWM, High performance IGBT output (cycle/duty continuous variable) timer
synchronous output event, input capture (Both edge available), real timer output control), double buffer compare register
Timer counter
8
:
16-bit
脳
1
(timer pulse output, event count, High accuracy PWM output (cycle/duty continuous variable) pulse width measurement,
input capture (Both edge available),
32-bit
cascade connected (Timer
7
,
8), 32-bitPWM
output, synchronous output
event), double buffer compare register
Timer counter
9
:
16-bit
脳
1
(timer pulse output, event count, High accuracy PWM output (cycle/duty continuous variable), pulse width
measurement, input capture (Both edge available), real timer output control), double buffer compare register
Timer counter A :
8-bit
脳
1
(event count, Serial transfer clock timer, clock for function (timer, serial, LCD))
Watchdog timer
飩?/div>
Serial interface
Serial
0
~
3
: UART (full duplex) / synchronous
脳
1
Serial
錛?/div>
: multi master I虜C / synchronous
脳
1
Serial
5
: I虜C slave
脳
1
2
systems (External request/internal event request/software request maximum transfer cycles are
255)
飩?/div>
DMA controller
飩?/div>
I/O Pins
I/O
86
common use, Speci鏗乪d pull-up/pull-down resistor available, Input/output selectable (bit-unit)
MAD00063AEM

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