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MN101EF02K Datasheet

  • MN101EF02K

  • MN101E02H

  • 3頁

  • PANASONIC

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MN101E02H
Type
Internal ROM type
ROM (byte)
RAM (byte)
Package (Lead-free)
Minimum Instruction
Execution Time
QFP084-P-1818E
100
ns (at
3.135
V to
3.465
V, normal-mode)
MN101E02H
Mask ROM
160K
16K
QFP084-P-1818E (ES (Engineering Sample) available)
100
ns
MN101EF02K
FLASH
飩?/div>
Interrupts
External (5 lines)
Internal (15 lines) : Timer
脳
4,
A/D
脳
1,
RESET
脳
1,
OSD
脳
1,
Serial
脳
2,
Teletext decoder
脳
2,
I虜C
脳
1,
Caption
脳
1,
Remote control
脳
1,
HSYNC
脳
1,
VSYNC
脳
1
8-bit
timer
脳
4
Watchdog timer : Time-out period is selectable.
I虜C
脳
1
: for multimaster mode, bus line (output) has
2
systems
Sync serial / UART
脳
1
飩?/div>
Timer Counter
飩?/div>
Serial interface
飩?/div>
Caption / Teletext Decoder
銉籅uilt-in
sync separator
脳
1
飩?/div>
I/O Pins
I/O
35
Common use
飩?/div>
A/D converter
飩?/div>
PWM
10-bit
脳
8-ch.
(with S/H)
8-bit
脳
4-ch.
,
14-bit
脳
1-ch.
Remote control reception
1-layer
display (graphics, characters, splits)
Remote control input discriminant circuit built-in, build-in NTSC/PAL (BGHIDK, M, N)/SECAM/NTSC443 video signal processing
circuit, built-in
3-line
comb 鏗乴ter (NTSC), built-in adaptive
2-line
comb 鏗乴ter (PAL), built-in teletext decoder
In-circuit Emulator
PX-PAC101E02-4W9J
飩?/div>
Special Ports
飩?/div>
CRTC
飩?/div>
Notes
飩?/div>
Development tools
MAD00040EEM

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