飩?/div>
Interrupts
RESET, Runaway, External
0
to
4,
Timer
0
to
3,
Timer
6,
Capstan FG, Control, HSW, Cylinder(Drum) FG, Servo V-sync,
Synchronous output, OSD, XDS, Serial
1,
Serial
2,
PWM
4,
OSD V-sync
Timer counter
0
:
8-bit
脳
1
(timer function)
Clock source................
1/4, 1/16
of system clock frequency
Interrupt source ........... over鏗俹w of timer counter
0
Timer counter
1
:
8-bit
脳
1
(timer function, linear timer counter function)
Clock source................
1/4
of system clock frequency; CTL signal
Interrupt source ........... over鏗俹w of timer counter
1
Timer counter
2
:
16-bit
脳
1
(timer function, input capture (CTL speci鏗乪d edge), duty judgment of CTL signal)
Clock source................
1/4, 1/16, 1/24
of system clock frequency
Interrupt source ........... over鏗俹w of timer counter
2;
input of CTL speci鏗乪d edge; under鏗俹w of timer
2
shift register
4-bit
counter;
coincidence of timer
2
shift register with timer
2
shift register compare register
Timer counter
3
:
16-bit
脳
1
(timer function)
Clock source................
1/4, 1/16
of system clock frequency
Interrupt source ........... over鏗俹w of timer counter
3
Timer counter
5
:
19-bit
脳
1
(watchdog, stable oscillation waiting function)
Clock source................ system clock
Watchdog interrupt source ...
1/2
16
,
1/2
19
of timer counter
5
frequency
Clear by stable oscillation ... after
256
counts by timer counter
5
(2
18
counts of OSC oscillation clock)
Timer counter
6
:
16-bit
脳
1
(clock function [max.
2
s])
Clock source................
1/512
of OSC oscillation clock frequency; XI oscillation clock;
1/8, 1/128
of system clock frequency
Interrupt source ...........
1/2
13
,
1/2
1
4
,
1/2
15
over鏗俹w of timer counter
6
飩?/div>
Timer Counter
飩?/div>
Serial interface
Serial
1
:
8-bit
脳
1
(synchronous type)
(transfer direction of MSB/LSB selectable, start condition function)
Clock source................
1/8, 1/16, 1/32, 1/64, 1/128, 1/256
of system clock frequency; NSBT1 pin input
Serial
2
:
8-bit
脳
1
(I虜C)
(master transmission/reception, slave transmission/reception)
Clock source................
1/144
to
1/252
of system clock; SCK pin input
MAD00033EEM
1
2
3
4
5
