飩?/div>
Interrupts
RESET, Runaway, External
0
to
4,
key input (P50 to P54), Timer
0
to
4,
Timer
6,
Timer
7,
Capstan FG, Control, HSW,
Cylinder(Drum) FG, Servo V-sync, Synchronous output, OSD, XDS, Serial
0
to
2,
A/D (common with PWM
4
reference frequency),
OSD V-sync
Timer counter
0
:
16-bit
脳
1
(timer function, clock function [max.
2
s or max.
36
h at cascade-connecting with timer
6])
Clock source................
1/2,
(1/4,)
1/8,
(1/16) of system clock frequency; over鏗俹w of timer counter
6; 1/512
of XI oscillation
clock or OSC oscillation clock frequency
Interrupt source ........... over鏗俹w of timer counter
0
Timer counter
1
:
16-bit
脳
1
(timer function, linear timer counter function)
Clock source................
1/2,
(1/4,)
1/8,
(1/16) of system clock frequency; CTL signal
Interrupt source ........... over鏗俹w of timer counter
1
Timer counter
2
:
16-bit
脳
1
(timer function, input capture
(DCTL speci鏗乪d edge), duty judgment of DCTL signal)
Clock source................
1/2,
(1/4,)
1/8,
(1/16,)
1/12,
(1/24) of system clock frequency
Interrupt source ........... over鏗俹w of timer counter
2;
input of DCTL speci鏗乪d edge; under鏗俹w of timer
2
shift register
4-bit
counter; coincidence of timer
2
shift register with timer
2
shift register compare register
Timer counter
3
:
16-bit
脳
1
(timer function, detection of serial indexing, generation of remote control output carrier frequency)
Clock source................
1/2,
(1/4,)
1/8,
(1/16) of system clock frequency; XI oscillation clock
Interrupt source ........... over鏗俹w of timer counter
3
Timer counter
4
:
16-bit
脳
1
(timer function, event count [P15 input], generation of serial transmission clock)
Clock source................
1/8,
(1/16) of system clock frequency; external clock input
Interrupt source ........... over鏗俹w of timer counter
4;
coincidence of timer counter
4
with OCR4
Timer counter
5
:
19-bit
脳
1
(watchdog, stable oscillation waiting function)
Clock source................ system clock
Watchdog interrupt source ...
1/2
16
,
1/2
19
of timer counter
5
frequency
Clear by stable oscillation ... after
256
counts by timer counter
5
(218 counts of OSC oscillation clock)
Timer counter
6
:
16-bit
脳
1
(clock function [max.
2
s])
Clock source................
1/512
of OSC oscillation clock frequency; XI oscillation clock;
1/4,
(1/8,)
1/64,
(1/128) of system clock
frequency
Interrupt source ...........
1/2
13
,
1/2
14
,
1/2
15
over鏗俹w of timer counter
6
Timer counter
7
:
8-bit
脳
1
or
4-bit
脳
2
(timer function, event count)
Clock source................
1/4,
(1/8,)
1/16,
(1/32) of system clock frequency; external clock input
Interrupt source ........... over鏗俹w of timer counter
7
(although when
4-bit
脳
2,
there is one interrupt vector. )
飩?/div>
Timer Counter
MAD00030GEM
1
2
3
4
5
