MN101D06F , MN101D06G , MN101D06H
Type
ROM (脳 8-bit)
脳
RAM (脳 8-bit)
脳
Package
Minimum Instruction
Execution Time
Interrupts
With main clock operated
When sub-clock operated
MN101D06F
96 K
3K
MN101D06G
128 K
4K
QFP100-P-1818B
*Lead-free
0.1397
碌s
(at 4.0 V to 5.5 V, 14.32 MHz)
71.5
碌s
(at 3.0 V to 5.5 V fixed to 14.32 MHz internal frequency division)
61
碌s
(at 2.2 V to 5.5 V, 32.768 kHz)
MN101D06H
160 K
5K
鈥?RESET 鈥?Runaway 鈥?External 0 鈥?External 1 鈥?External 2 鈥?External 3 鈥?External 4 鈥?key input (P50 to 54)
鈥?Timer 0 鈥?Timer 1 鈥?Timer 2 鈥?Timer 3 鈥?Timer 4 鈥?Timer 6 鈥?Capstan FG 鈥?Control 鈥?HSW
鈥?Cylinder(Drum) FG 鈥?Servo V-sync 鈥?Synchronous output 鈥?OSD 鈥?XDS 鈥?Serial 0 鈥?Serial 1 鈥?Serial 2
鈥?A/D (common with PWM 4 reference frequency) 鈥?OSD V-sync
Timer counter 0: 16-bit
脳
1
(timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6])
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/2, (1/4,) 1/8, (1/16) of system clock frequency; overflow of timer counter 6;
1/512 of XI oscillation clock or OSC oscillation clock frequency
Interrupt source 路路路路路路路路路路路路路路路路 overflow of timer counter 0
Timer counter 1: 16-bit
脳
1 (timer function, linear timer counter function)
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/2, (1/4,) 1/8, (1/16) of system clock frequency; CTL signal
Interrupt source 路路路路路路路路路路路路路路路路 overflow of timer counter 1
Timer counter 2: 16-bit
脳
1 (timer function, input capture, duty judgment of CTL signal(VISS/VASS detection function))
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/2, (1/4,) 1/8, (1/16,) 1/12, (1/24) of system clock frequency
Interrupt source 路路路路路路路路路路路路路路路路 overflow of timer counter 2; input of CTL specified edge; underflow of timer 2
shift register 4-bit counter; coincidence of timer 2 shift register with timer 2
shift register compare register
Timer counter 3: 16-bit
脳
1
(timer function, detection of serial indexing, generation of remote control output carrier frequency)
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/2, (1/4,) 1/8, (1/16) of system clock frequency; XI oscillation clock
Interrupt source 路路路路路路路路路路路路路路路路 overflow of timer counter 3
Timer counter 4: 16-bit
脳
1 (timer function, event count [P15 input], generation of serial transmission clock)
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/8, (1/16) of system clock frequency; external clock input
Interrupt source 路路路路路路路路路路路路路路路路 overflow of timer counter 4; coincidence of timer counter 4 with OCR4
Timer counter 5: 19-bit
脳
1 (watchdog, stable oscillation waiting function)
Clock source 路路路路路路路路路路路路路路路路路路路路路 system clock
Watchdog interrupt source 路路 1/2
16
, 1/2
19
of timer counter 5 frequency
Clear by stable oscillation 路路 after 256 counts by timer counter 5 (2
18
counts of OSC oscillation clock)
Timer counter 6: 16-bit
脳
1 (clock function [max. 2 s])
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/512 of OSC oscillation clock frequency; XI oscillation clock;
1/4, (1/8,) 1/64, (1/128) of system clock frequency
Interrupt source 路路路路路路路路路路路路路路路路 1/2
13
, 1/2
14
, 1/2
15
overflow of timer counter 6
Timer counter 7: 8-bit
脳
1 or 4-bit
脳
2 (timer function, event count)
Clock source 路路路路路路路路路路路路路路路路路路路路路 1/4, (1/8,) 1/16, (1/32) of system clock frequency; external clock input
Interrupt source 路路路路路路路路路路路路路路路路 overflow of timer counter 7 (although when 4-bit
脳
2, there is one interrupt vector. )
Timer Counter
Serial Interface
Serial 0: 8-bit
脳
1 (synchronous type/start-stop synchronous type) (transfer direction of MSB/LSB selectable)
Synchronous type clock source 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency;
2-division timer 4 output; NSBT0 pin input
Clock for UART 路路路路路路路路路路路路路路 8-division of above clock; 2-division timer 4 output; NSBT0 pin input
MAD00029FEM
1
2
3
4
5
