V.
飩?/div>
Interrupts
RESET, Watchdog, External
0
to
2,
Timer
0
to
5,
Time base, Serial
0,
A/D conversion 鏗乶ish
Timer counter
0
:
8-bit
脳
1
(square-wave/8-bit PWM output, event count, generation of remote control carrier)
Clock source................
1/1, 1/4
of system clock frequency;
1/1
of OSC oscillation clock frequency; external clock input
Interrupt source ........... coincidence with compare register
0
Timer counter
1
:
8-bit
脳
1
(square-wave output, event count, synchronous output event)
Clock source................
1/16, 1/64
of system clock frequency; external clock input
Interrupt source ........... coincidence with compare register
1
Timer counter
0, 1
can be cascade-connected.
Timer counter
2
:
8-bit
脳
1
(square-wave/8-bit PWM output, event count, synchronous output event)
Clock source................
1/1, 1/4
of system clock frequency; external clock input
Interrupt source ........... coincidence with compare register
2
Timer counter
3
:
8-bit
脳
1
(square-wave output, event count, generation of remote control carrier, serial
0
baud rate timer)
Clock source................
1/4, 1/16
of system clock frequency;
1/1
of OSC oscillation clock frequency; external clock input
Interrupt source ........... coincidence with compare register
3
Timer counter
2, 3
can be cascade-connected.
Timer counter
4
:
16-bit
脳
1
(square-wave/16-bit PWM output, event count, synchronous output event, input capture)
Clock source................
1/4, 1/16
of system clock frequency;
1/1
of OSC oscillation clock frequency; external clock input
Interrupt source ........... coincidence with compare register
4
Time base timer (one-minute count setting, independently operable
8-bit
timer counter
5)
Clock source................
1/4
of system clock frequency;
1/1, 1/8192
of OSC oscillation clock frequency
Interrupt source ........... coincidence with compare register
5; 1/8192
prescaler over鏗俹w
Watchdog timer
Interrupt source ...........
1/1048576
of system clock frequency
飩?/div>
Timer Counter
飩?/div>
Serial interface
Serial
0
: synchronous type/simple UART (half-duplex)
脳
1
Clock source................
1/2, 1/4, 1/16
of system clock frequency; output of timer counter
3
飩?/div>
I/O Pins
I/O
Input
26
11
Common use :
17,
Speci鏗乪d pull-up resistor available
Input/output selectable (bit unit) :
26
Common use, Speci鏗乪d pull-up resistor available
飩?/div>
A/D converter
飩?/div>
Special Ports
10-bit
脳
8-ch.
(with S/H)
Buzzer output, remote control carrier signal output, high-current drive port
MAD00052CEM
next
MN101CF94D相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
LOW POWER QUINT DIFFERENTIAL LINE RECEIVER
NSC
-
英文版
LOW POWER QUINT DIFFERENTIAL LINE RECEIVER
NSC [Natio...
-
英文版
MN101C15
ETC
-
英文版
MN101C15
ETC [ETC]
-
英文版
Microcomputers/Controllers
PANASONIC
-
英文版
Microcomputers/Controllers
PANASONIC ...
-
英文版
The lower limit for operation guarantee for EPROM built-in t...
PANASONIC
-
英文版
The lower limit for operation guarantee for EPROM built-in t...
PANASONIC ...
-
英文版
Timer Counter
PANASONIC
-
英文版
Timer Counter
PANASONIC ...
-
英文版
Remote control input discriminant circuit built-in
PANASONIC
-
英文版
Remote control input discriminant circuit built-in
PANASONIC ...
-
英文版
Lower limit for operation guarantee for flash memory built-i...
PANASONIC
-
英文版
Lower limit for operation guarantee for flash memory built-i...
PANASONIC ...
-
英文版
Timer counter 0 : 8-bit X 1
PANASONIC
-
英文版
Timer counter 0 : 8-bit X 1
PANASONIC ...
-
英文版
The lower limit for operation guarantee for flash memory bui...
PANASONIC
-
英文版
The lower limit for operation guarantee for flash memory bui...
PANASONIC ...
-
英文版
MN101C67D
PANASONIC
-
英文版
MN101C67D
PANASONIC ...