鈩?/div>
SO-8 for Surface Mount
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
TMOS V is a new technology designed to achieve an on鈥搑esis-
tance area product about one鈥揾alf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E鈥揊ET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
鈥?/div>
On鈥搑esistance Area Product about One鈥揾alf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
鈥?/div>
Faster Switching than E鈥揊ET Predecessors
G
S
MMDF2N06VL
DUAL TMOS MOSFET
2.5 AMPERES
60 VOLTS
RDS(on) = 0.130 OHM
TM
D
CASE 751鈥?5, Style 11
SO鈥?
Source鈥?
1
2
3
4
8
7
6
5
Drain鈥?
Drain鈥?
Drain鈥?
Drain鈥?
Features Common to TMOS V and TMOS E鈥揊ETS
鈥?/div>
Avalanche Energy Specified
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Static Parameters are the Same for both TMOS V and TMOS E鈥揊ET
鈥?/div>
Miniature SO鈥? Surface Mount Package 鈥?Saves Board Space
鈥?/div>
Mounting Information for SO鈥? Package Provided
MAXIMUM RATINGS
(TJ = 25擄C unless otherwise noted)
Rating
Drain鈥搕o鈥揝ource Voltage
Drain鈥搕o鈥揋ate Voltage, (RGS = 1 M鈩?
Gate鈥搕o鈥揝ource Voltage 鈥?Continuous
Drain Current 鈥?Continuous @ TA = 25擄C
Drain Current
鈥?Continuous @ TA = 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation @ TA = 25擄C (1)
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25
鈩?
Thermal Resistance, Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 0.0625鈥?from case for 10 seconds
Gate鈥?
Source鈥?
Gate鈥?
Top View
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
R
胃JA
TL
Value
60
60
鹵
15
2.5
0.5
7.5
2.0
鈥?55 to 175
54
62.5
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
W
擄C
mJ
擄C/W
擄C
DEVICE MARKING
2N6VL
(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.
ORDERING INFORMATION
Device
MMDF2N06VLR1
MMDF2N06VLR2
Reel Size
7鈥?/div>
13鈥?/div>
Tape Width
12mm embossed tape
12mm embossed tape
Quantity
500
2500
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E鈥揊ET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
漏
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
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