MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register
February 1984
Revised February 1999
MM74HCT164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HCT164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low con-
sumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky devices.
This 8-bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A
LOW at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock
pulse. A HIGH level on one input enables the other input
which will then determine the state of the first flip-flop. Data
at the serial inputs may be changed while the clock is HIGH
or LOW, but only information meeting the setup and hold
time requirements will be entered. Data is serially shifted in
and out of the 8-bit register during the positive going transi-
tion of the clock pulse. Clear is independent of the clock
and accomplished by a low level at the CLEAR input.
The 74HCT logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
Typical propagation delay: 20 ns
s
Low quiescent current: 40
碌A
maximum (74HCT Series)
s
Low input current: 1
碌A
maximum
s
Fanout of 10 LS-TTL loads
s
TTL input compatible
Ordering Code:
Order Number
MM74HCT164M
MM74HCT164SJ
MM74HCT164N
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Truth Table
Inputs
Clear
L
H
H
H
H
Clock
X
L
鈫?/div>
鈫?/div>
鈫?/div>
A
X
X
H
L
X
B
X
X
H
X
L
Q
A
L
Q
AO
H
L
L
Outputs
Q
B
L
Q
BO
Q
An
Q
An
Q
An
...
Q
H
L
Q
HO
Q
Gn
Q
Gn
Q
Gn
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Irrelevant (any input, including transitions)
鈫?=
Transition from LOW-to-HIGH level.
Q
AO
, Q
BO
, Q
HO
=
the level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady state input conditions were established.
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
before the most recent
鈫?/div>
transition of
the clock; indicated a one-bit shift.
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005765.prf
www.fairchildsemi.com
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