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MM74HCT14_05 Datasheet

  • MM74HCT14_05

  • Hex Inverting Schmitt Trigger

  • 7頁

  • FAIRCHILD

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MM74HCT14 Hex Inverting Schmitt Trigger
September 1983
Revised January 2005
MM74HCT14
Hex Inverting Schmitt Trigger
General Description
The MM74HCT14 utilizes advanced silicon-gate CMOS
technology to achieve the low power dissipation and high
noise immunity of standard CMOS, as well as the capability
to drive 10 LS-TTL loads.
The 74HCT logic family is functionally and pinout compati-
ble with the standard 74LS logic family. All inputs are pro-
tected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 13 ns
s
Wide power supply range: 2鈥?V
s
Low quiescent current: 10
碌
A maximum
s
Low input current: 1
碌
A maximum
s
Fanout of 10 LS-TTL loads
s
Typical hysteresis voltage: 0.9V at V
CC
=
4.5V
s
TTL, LS pin-out and input threshold compatible
Ordering Codes:
Order Number
MM74HCT14M
MM74HCT14MX_NL
MM74HCT14SJ
MM74HCT14MTC
MM74HCT14N
Package
Number
M14A
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Schematic Diagram
Top View
漏 2005 Fairchild Semiconductor Corporation
DS500059
www.fairchildsemi.com

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