MM54HCT109 MM74HCT109 Dual J-K Flip-Flops with Preset and Clear
January 1988
MM54HCT109 MM74HCT109
Dual J-K Flip-Flops with Preset and Clear
General Description
These high speed J-K FLIP-FLOPS utilize advanced silicon-
gate CMOS technology They possess the low power con-
sumption and high noise immunity of standard CMOS inte-
grated circuits along with the ability to drive 10 LS-TTL
loads
Each flip flop has independent J K PRESET CLEAR and
CLOCK inputs and Q and Q outputs These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input
The 54HCT 74HCT logic family is functionally as well as
pin-out compatible with the standard 54LS 74LS logic fami-
ly All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
MM54HCT MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs
Features
Y
Y
Y
Y
Typical propagation delay 20 ns
Low input current 1
mA
maximum
Low quiescent current 40
mA
maximum (74HCT Series)
Output drive capability 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Outputs
Q
Q
u
u
u
u
L
H
L
L
H
H
H
L
H
TOGGLE
Q0
Q0
H
L
Q0
Q0
Order Number MM54HCT109 or MM74HCT109
TL F 5361 鈥?1
TL F 5361 鈥?2
C
1995 National Semiconductor Corporation
TL F 5361
RRD-B30M105 Printed in U S A
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