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MM74HC86 Datasheet

  • MM74HC86

  • Quad 2-Input Exclusive OR Gate

  • Fairchild

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MM74HC86 Quad 2-Input Exclusive OR Gate
September 1983
Revised January 2005
MM74HC86
Quad 2-Input Exclusive OR Gate
General Description
The MM74HC86 EXCLUSIVE OR gate utilizes advanced
silicon-gate CMOS technology to achieve operating
speeds similar to equivalent LS-TTL gates while maintain-
ing the low power consumption and high noise immunity
characteristic of standard CMOS integrated circuits. These
gates are fully buffered and have a fanout of 10 LS-TTL
loads. The 74HC logic family is functionally as well as pin
out compatible with the standard 74LS logic family. All
inputs are protected from damage due to static discharge
by internal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 9 ns
s
Wide operating voltage range: 2鈥?V
s
Low input current: 1
碌
A maximum
s
Low quiescent current: 20
碌
A maximum (74 Series)
s
Output drive capability: 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC86M
MM74HC86MX_NL
MM74HC86SJ
MM74HC86MTC
MM74HC86N
MM74HC86NX_NL
Package
Number
M14A
M14A
M14D
MTC14
N14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Inputs
A
L
L
H
H
Y
=
A
鈯?/div>
B
=
A B
+
AB
Outputs
B
L
H
L
H
Y
L
H
H
L
Top View
漏 2005 Fairchild Semiconductor Corporation
DS005305
www.fairchildsemi.com

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MM74HC86

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