MM54HC75 MM74HC75 4-Bit Bistable Latch with Q and Q Output
January 1988
MM54HC75 MM74HC75
4-Bit Bistable Latch with Q and Q Output
General Description
This 4-bit latch utilizes advanced silicon-gate CMOS tech-
nology to achieve the high noise immunity and low power
consumption normally associated with standard CMOS inte-
grated circuits These devices can drive 10 LS-TTL loads
This latch is ideally suited for use as temporary storage for
binary information processing input output and indicator
units Information present at the data (D) input is transferred
to the Q output when the enable (G) is high The Q output
will follow the data input as long as the enable remains high
When the enable goes low the information that was present
at the data input at the time the transition occurred is re-
tained at the Q output until the enable is permitted to go
high again
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Y
Typical operating frequency 50 MHz
Typical propagation delay 12 ns
Wide operating supply voltage range 2 鈥?6V
Low input current 1
mA
maximum
Low quiescent supply current 80
mA
maximum
(74HC Series)
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Truth Table
Inputs
D
L
H
X
G
H
H
L
Outputs
Q
L
H
Q
0
Q
H
L
Q
0
H
e
High Level L
e
Low Level
X
e
Don鈥檛 Care
Q
0
e
The level of Q before the transition of G
TL F 5303 鈥?1
Order Number MM54HC75 or MM74HC75
(1 of 4 latches)
TL F 5303 鈥?2
C
1995 National Semiconductor Corporation
TL F 5303
RRD-B30M105 Printed in U S A
1
2
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