MM54HC595 MM74HC595 8-Bit Shift Registers with Output Latches
January 1988
MM54HC595 MM74HC595
8-Bit Shift Registers with Output Latches
General Description
This high speed shift register utilizes advanced silicon-gate
CMOS technology This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits as well as the ability to drive 15 LS-TTL
loads
This device contains an 8-bit serial-in parallel-out shift reg-
ister that feeds an 8-bit D-type storage register The storage
register has 8 TRI-STATE outputs Separate clocks are
provided for both the shift register and the storage register
The shift register has a direct-overriding clear serial input
and serial output (standard) pins for cascading Both the
shift register and storage register use positive-edge trig-
gered clocks If both clocks are connected together the
shift register state will always be one clock pulse ahead of
the storage register
The 54HC 74HC logic family is speed function and pin-out
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Y
Y
Low quiescent current 80
mA
maximum (74HC Series)
Low input current 1
mA
maximum
8-bit serial-in parallel-out shift register
with storage
Wide operating voltage range 2V 鈥?6V
Cascadable
Shift register has direct clear
Guaranteed shift frequency DC to 30 MHz
Connection Diagram
Dual-In-Line Package
Truth Table
RCK
X
X
X
SCK
X
X
SCLR
X
L
H
H
G
H
L
L
L
Function
Q
A
thru Q
H
e
TRI STATE
Shift Register cleared
Q
H
e
Shift Register clocked
Q
N
e
Q
n
Q
e
SER
Contents of Shift
Register transferred
to output latches
u
X
u
TL F 5342 鈥?1
Top View
Order Number MM54HC595 or MM74HC595
TRI-STATE is a registered trademark of National Semiconductor Corp
C
1995 National Semiconductor Corporation
TL F 5342
RRD-B30M105 Printed in U S A
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