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MM74HC51J Datasheet

  • MM74HC51J

  • National Semiconductor [Dual AND-OR-Invert Gate / Dual AND-...

  • NSC

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MM54HC51 MM74HC51 Dual AND-OR-Invert Gate
MM54HC58 MM74HC58 Dual AND-OR Gate
January 1988
MM54HC51 MM74HC51 Dual AND-OR-Invert Gate
MM54HC58 MM74HC58 Dual AND-OR Gate
General Description
These gates utilize advanced silicon-gate CMOS technology
to achieve operating speeds similar to LS-TTL gates with
the low power consumption of standard CMOS integrated
circuits All gates have buffered outputs providing high
noise immunity and the ability to drive 10 LS-TTL loads The
54HC 74HC logic family is functionally as well as pin-out
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical propagation delay 10 ns
Wide power supply range 2 鈥?6V
Low quiescent supply current 20
mA
maximum
(74 Series)
Low input current 1
mA
maximum
High output current 4 mA minimum
Connection Diagrams
Dual-In-Line Package
TL F 5302 鈥?1
Top View
Order Number MM54HC51 or MM74HC51
Dual-In-Line Package
TL F 5302 鈥?2
Top View
Order Number MM54HC58 or MM74HC58
C
1995 National Semiconductor Corporation
TL F 5302
RRD-B30M105 Printed in U S A

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