MM54HC42 MM74HC42 BCD-to-Decimal Decoder
January 1988
MM54HC42 MM74HC42
BCD-to-Decimal Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol-
ogy Data on the four input pins select one of the 10 outputs
corresponding to the value of the BCD number on the in-
puts An output will go low when selected otherwise it re-
mains high If the input data is not a valid BCD number all
outputs will remain high The circuit has high noise immunity
and low power consumption usually associated with CMOS
circuitry yet also has speeds comparable to low power
Schottky TTL (LS-TTL) circuits and is capable of driving 10
LS-TTL equivalent loads
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground
Features
Y
Y
Y
Y
Typical propagation delay 15 ns
Wide supply range 2V 鈥?6V
Low quiescent current 80
mA
(74HC)
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-in-line Package
Truth Table
No
Inputs
D C B A 0
L L
L L
L L
L L
L H
L
L
L
H
H
H
H
H
INVALID
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
Outputs
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
TL F 5301 鈥?1
Top View
Order Number MM54HC42 or MM74HC42
H
e
High Level L
e
Low Level
Logic Diagram
TL F 5301 鈥?2
C
1995 National Semiconductor Corporation
TL F 5301
RRD-B30M105 Printed in U S A
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