MM74HC374 3-STATE Octal D-Type Flip-Flop
September 1983
Revised February 1999
MM74HC374
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HC374 high speed Octal D-Type Flip-Flops uti-
lize advanced silicon-gate CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the setup and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 20 ns
s
Wide operating voltage range: 2鈥?V
s
Low input current: 1
碌A
maximum
s
Low quiescent current: 80
碌A
maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
MM74HC374WM
MM74HC374SJ
MM74HC374MTC
MM74HC374N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Output
Control
L
L
L
H
鈫?/div>
鈫?/div>
L
X
H
L
X
X
H
L
Q
0
Z
Clock
Data
Output
Top View
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
鈫?=
Transition from LOW-to-HIGH
Z
=
High Impedance State
Q
0
=
The level of the output before steady state input conditions were
established
漏 1999 Fairchild Semiconductor Corporation
DS005336.prf
www.fairchildsemi.com
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