MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
September 1983
Revised February 1999
MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
The MM74HC259 device utilizes advanced silicon-gate
CMOS technology to implement an 8-bit addressable latch,
designed for general purpose storage applications in digital
systems.
The MM74HC259 has a single data input (D), 8 latch out-
puts (Q1鈥換8), 3 address inputs (A, B, and C), a common
enable input (G), and a common CLEAR input. To operate
this device as an addressable latch, data is held on the D
input, and the address of the latch into which the data is to
be entered is held on the A, B, and C inputs. When
ENABLE is taken LOW the data flows through to the
addressed output. The data is stored when ENABLE transi-
tions from LOW-to-HIGH. All unaddressed latches will
remain unaffected. With enable in the HIGH state the
device is deselected, and all latches remain in their previ-
ous state, unaffected by changes on the data or address
inputs. To eliminate the possibility of entering erroneous
data into the latches, the enable should be held HIGH
(inactive) while the address lines are changing.
If enable is held HIGH and CLEAR is taken LOW all eight
latches are cleared to a LOW state. If enable is LOW all
latches except the addressed latch will be cleared. The
addressed latch will instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide supply range: 2鈥?V
s
Low input current: 1
碌A
maximum
s
Low quiescent current: 80
碌A
maximum (74HC Series)
Ordering Code:
Order Number
MM74HC259M
MM74HC259SJ
MM74HC259MTC
MM74HC259N
Package Number Package Description
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Latch Selection Table
Select Inputs
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Latch
Addressed
0
1
2
3
4
5
6
7
Top View
H
=
HIGH level, L
=
LOW level
D
=
the level at the data input
Q
i0
the level of Q
i
(i
=
0, 1 ...7, as appropriate)
before the indicated steady-state input
conditions were established.
漏 1999 Fairchild Semiconductor Corporation
DS005006.prf
www.fairchildsemi.com
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