MM74HC240 Inverting Octal 3-STATE Buffer
September 1983
Revised August 2000
MM74HC240
Inverting Octal 3-STATE Buffer
General Description
The MM74HC240 3-STATE buffer utilizes advanced sili-
con-gate CMOS technology. It possesses high drive cur-
rent outputs which enable high speed operation even when
driving large bus capacitances. These circuits achieve
speeds comparable to low power Schottky devices, while
retaining the advantage of CMOS circuitry, i.e., high noise
immunity and low power consumption. It has a fanout of 15
LS-TTL equivalent inputs.
The MM74HC240 is an inverting buffer and has two active
LOW enables (1G and 2G). Each enable independently
controls 4 buffers.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 12 ns
s
3-STATE outputs for connection to system buses
s
Wide power supply range: 2鈥?V
s
Low quiescent supply current: 80
碌
A (74 Series)
s
Output current: 6 mA
Ordering Code:
Order Number
MM74HC240WM
MM74HC240SJ
MM74HC240MTC
MM74HC240N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Truth Table
1G
L
L
H
H
H
=
HIGH Level
L
=
LOW Level
Z
=
HIGH Impedance
1A
L
H
L
H
1Y
H
L
Z
Z
2G
L
L
H
H
2A
L
H
L
H
2Y
H
L
Z
Z
Top View
漏 2000 Fairchild Semiconductor Corporation
DS005020
www.fairchildsemi.com