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MM74HC237M/A+ Datasheet

  • MM74HC237M/A+

  • IC,DECODER/DEMUX,3-TO-8-LINE,HC-CMOS,SOP,16PIN,PLASTIC

  • 147.94KB

  • 6頁(yè)

  • NSC

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MM54HC237 MM74HC237 3-to-8 Line Decoder With Address Latches
January 1988
MM54HC237 MM74HC237
3-to-8 Line Decoder With Address Latches
General Description
These devices utilize advanced silicon-gate CMOS technol-
ogy to implement a three-to-eight line decoder with latches
on the three address inputs When GL goes from low to
high the address present at the select inputs (A B and C) is
stored in the latches As long as GL remains high no ad-
dress changes will be recognized Output enable controls
G1 and G2 control the state of the outputs independently of
the select or latch-enable inputs All of the outputs are low
unless G1 is high and G2 is low The 鈥橦C237 is ideally suit-
ed for the implementation of glitch-free decoders in stored-
address applications in bus oriented systems
The 54HC 74HC logic family is speed function and pin-out
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
diodes to V
CC
and ground
Features
Y
Y
Y
Y
Typical propagation delay 20 ns
Wide supply range 2 鈥?6V
Latched inputs for easy interfacing
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL F 5326 鈥?1
Top View
Order Number MM54HC237 or MM74HC237
Truth Table
INPUTS
ENABLE
X
X
L
L
L
L
L
L
L
L
H
X
L
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
SELECT
X
X
L
L
L
L
X
X
X
X
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
OUTPUTS
GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
L L
L H
H L
H H
H L L
H L H
H H L
H H H
X
X
X
Output corresponding to stored
address L all others H
H
e
high level L
e
low level X
e
irrelevant
C
1995 National Semiconductor Corporation
TL F 5326
RRD-B30M105 Printed in U S A

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