MM54HC155 MM74HC155 Dual 2-To-4 Line Decoder Demultiplexers
January 1988
MM54HC155 MM74HC155 Dual 2-To-4
Line Decoder Demultiplexers
General Description
The MM54HC155 MM74HC155 is a high speed silicon-gate
CMOS decoder demultiplexer It utilizes advanced silicon-
gate CMOS technology and features dual 1-line-to-4-line
demultiplexers with independent strobes and common bina-
ry-address inputs When both sections are enabled by the
strobes the common address inputs sequentially select and
route associated input data to the appropriate output of
each section The individual strobes permit activating or in-
hibiting each of the 4-bit sections as desired Data applied
to input C1 is inverted at its outputs and data applied to C2
is non-inverted at its outputs The inverter following the C1
data input permits use as a 3-to-8-line decoder or 1-to-8-
line demultiplexer without gating
All inputs to the decoder are protected from damage due to
electrostatic discharge by diodes to V
CC
and Ground
The device is capable of driving 10 low power Schottky TTL
equivalent loads
The MM54HC155 MM74HC155 is functionally and pin
equivalent to the 54LS155 74LS155 with the advantage of
reduced power consumption
Features
Y
Y
Y
Y
Applications
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer
Typical propagation delay 22 ns
Low quiescent current 80
mA
maximum
(74HC series)
Wide operating range 2V 鈥?6V
Connect and Logic Diagram
Truth Tables
Inputs
Select
B
X
L
L
H
H
X
A
X
L
H
L
H
X
Strobe
G1
H
L
L
L
L
X
Inputs
Select
B
X
L
L
H
H
X
A
X
L
H
L
H
X
Strobe
G2
H
L
L
L
L
X
2-to-4-Line Decoder
or 1-Line to 4-line Demultiplexer
Outputs
Data
C1
X
H
H
H
H
L
1Y0
H
L
H
H
H
H
1Y1
H
H
L
H
H
H
1Y2
H
H
H
L
H
H
1Y3
H
H
H
H
L
H
Outputs
Data
C2
X
L
L
L
L
H
2Y0
H
L
H
H
H
H
2Y1
H
H
L
H
H
H
2Y2
H
H
H
L
H
H
2Y3
H
H
H
H
L
H
TL F 8364 鈥?1
Order Number MM54HC155 or
MM74HC155
3-Line-to-8-Line Decoder
or 1-Line-to-8-Line Demultiplexer
Inputs
Select
IC B A
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
Strobe
(0)
Or Data
IG
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
(1)
(2)
Outputs
(3)
(4)
(5)
(6)
(7)
2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
IC
e
inputs C1 and C2 connected together
IG
e
inputs G1 and G2 connected together
H
e
high level L
e
low level X
e
don鈥檛 care
C
1995 National Semiconductor Corporation
TL F 8364
RRD-B30M105 Printed in U S A
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