MM54HC153 MM74HC153 Dual 4-Input Multiplexer
January 1988
MM54HC153 MM74HC153
Dual 4-Input Multiplexer
General Description
This 4-to-1 line multiplexer utilizes advanced silicon-gate
CMOS technology It has the low power consumption and
high noise immunity of standard CMOS integrated circuits
This device is fully buffered allowing it to drive 10 LS-TTL
loads Information on the data inputs of each multiplexer is
selected by the address on the A and B inputs and is pre-
sented on the Y outputs Each multiplexer possesses a
strobe input which enables it when taken to a low logic lev-
el When a high logic level is applied to a strobe input the
output of its associated multiplexer is taken low
The 54HC 74HC logic family is functionally and pinout com-
patible with the standard 54LS 74LS logic family All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical propagation delay 24 ns
Wide power supply range 2V 鈥?6V
Low quiescent current 80
mA
maximum (74HC Series)
Low input current 1
mA
maximum
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL F 5107 鈥?1
Top View
Order Number MM54HC153 or MM74HC153
Truth Table
Select
Inputs
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
C0
X
L
H
X
X
X
X
X
X
Data Inputs
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
C3
X
X
X
X
X
X
X
L
H
Strobe
G
H
L
L
L
L
L
L
L
L
Output
Y
L
L
H
L
H
L
H
L
H
Select inputs A and B are common to both sections
H
e
high level L
e
low level X
e
don鈥檛 care
C
1995 National Semiconductor Corporation
TL F 5107
RRD-B30M105 Printed in U S A
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