MM74C73 鈥?MM74C76 Dual J-K Flip-Flops with Clear and Preset
October 1987
Revised January 1999
MM74C73 鈥?MM74C76
Dual J-K Flip-Flops with Clear and Preset
General Description
The MM74C73 and MM74C76 dual J-K flip-flops are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement transistors.
Each flip-flop has independent J, K, clock and clear inputs
and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and are supplied in 16 pin packages. This
flip-flop is edge sensitive to the clock input and change
state on the negative going transition of the clock pulse.
Clear or preset is independent of the clock and is accom-
plished by a low level on the respective input.
Features
s
Supply voltage range:
s
High noise immunity:
3V to 15V
Drive 2 LPTTL loads
0.45 V
CC
(typ.)
s
Tenth power TTL compatible:
s
Low power: 50 nW (typ.)
s
Medium speed operation: 10 MHz (typ.)
Applications
鈥?Automotive
鈥?Data terminals
鈥?Instrumentation
鈥?Medical electronics
鈥?Alarm systems
鈥?Industrial electronics
鈥?Remote metering
鈥?Computers
Ordering Code:
Order Number
MM74C73N
MM74C76M
MM74C76N
Package Number
N14A
M16A
N16E
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150鈥?Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
MM74C73
MM74C76
Note:
A logic 鈥?鈥?on clear sets Q to a logic 鈥?鈥?
Note:
A logic 鈥?鈥?on preset sets Q to a logic 鈥?鈥?
Note:
A logic 鈥?鈥?on clear sets Q to logic 鈥?鈥?
Top View
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005884.prf
www.fairchildsemi.com