MM74C175 Quad D-Type Flip-Flop
October 1987
Revised January 1999
MM74C175
Quad D-Type Flip-Flop
General Description
The MM74C175 consists of four positive-edge triggered D-
type flip-flops implemented with monolithic CMOS technol-
ogy. Both are true and complemented outputs from each
flip-flop are externally available. All four flip-flops are con-
trolled by a common clock and a common clear. Informa-
tion at the D-type inputs meeting the set-up time
requirements is transferred to the Q outputs on the posi-
tive-going edge of the clock pulse. The clearing operation,
enabled by a negative pulse at Clear input, clears all four Q
outputs to logical 鈥?鈥?and Q's to logical 鈥?鈥?
All inputs are protected from static discharge by diode
clamps to V
CC
and GND.
Features
s
Wide supply voltage range:
s
Guaranteed noise margin:
s
High noise immunity:
3V to 15V
1.0V
0.45 V
CC
(typ.)
Fan out of 2 driving 74L
s
Low power TTL compatibility:
Ordering Code:
Order Number
MM74C175M
MM74C175N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150鈥?Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Each Flip-Flop
Inputs
Clear
L
H
H
H
H
Clock
X
鈫?/div>
鈫?/div>
H
L
D
X
H
L
X
X
Outputs
Q
L
H
L
NC
NC
Q
H
L
H
NC
NC
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
鈫?=
Transition from LOW-to-HIGH level
NC
=
No Change
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005900.prf
www.fairchildsemi.com
next