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MM74C08N Datasheet

  • MM74C08N

  • Quad 2-Input AND Gate

  • 49.29KB

  • 4頁

  • FAIRCHILD

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MM74C08 Quad 2-Input AND Gate
October 1987
Revised January 2004
MM74C08
Quad 2-Input AND Gate
General Description
The MM74C08 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin, these
gates provide basic functions used in the implementation of
digital integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swing essentially equal to the supply volt-
age. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
CC
and GND.
Features
s
Wide supply voltage range:
3.0V to 15V
s
Guaranteed noise margin: 1.0V
s
High noise immunity: 0.45 V
CC
(typ.)
s
Low power TTL compatibility:
Fan out of 2 driving 74L
s
Low power consumption: 10 nW/package (typ.)
Ordering Code:
Order Number
MM74CD8N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
Truth Table
Inputs
A
L
L
H
H
H
=
HIGH Level
L
=
LOW Level
Outputs
B
L
H
L
H
Y
L
L
L
H
Top View
漏 2004 Fairchild Semiconductor Corporation
DS005878
www.fairchildsemi.com

MM74C08N 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74C

  • 與門

  • 4

  • 2

  • -

  • 3 V ~ 15 V

  • -

  • 8mA，8mA

  • 1.5 V ~ 2 V

  • 3.5 V ~ 8 V

  • 70ns @ 10V，50pF

  • -55°C ~ 125°C

  • 通孔

  • 14-DIP

  • 14-DIP（0.300"，7.62mm）

  • 管件

  • 74C0874C08N

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