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MLS9203-01815 Datasheet

  • MLS9203-01815

  • Surface Mount Frequency Synthesizer CDMA 1780 - 1850 MHz

  • 86.30KB

  • 2頁

  • MA-COM

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Surface Mount Frequency Synthesizer
MLS9203-01815
MLS9203-01815
Surface Mount Frequency Synthesizer
CDMA 1780 - 1850 MHz
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Integrated VCO/PLL
Miniature SMT Package
Low Phase Noise
+5V Operation
12 Lead Package
12
11
10
9
8
7
DETAIL A
M/ A- COM LTD
DATE CODE
Description
The MLS9203-01815 synthesizer design integrates a high perfor-
mance buffered VCO, PLL circuit and discrete loop filter in a
surface mount package. The SMT packaging provides electrical
shielding, easy PCB assembly and repeatable performance. The
synthesiser is designed for use in PCS CDMA base stations and is
optimised for coverage of the PCS band with 50 kHz step size and
low phase noise.
M/A-COM synthesizers are manufactured in an ISO 9001 certi-
fied facility, incorporating surface mount assembly and automated
electrical testing. This ensures consistent electrical performance
and quality over volume production quantities.
1
IDENT
2
3
4
5
6
0.2
12.0
PART NO.
0.6
6.0 MAX
0.8
1.0
2.0
TYP.in 5 POSITIONS
13.2
DETAIL A
Electrical Specifications , T
A
= +25擄C, V
CC
= +5V,
鈭?/div>
F = 50 kHz, F
R
= 15 MHz
(unless otherwise stated)
1
Parameter
Frequency Range (F
OUT
)
RF Output Power (P
OUT
)
Harmonic Output
Spurious Output
Phase Noise
4
2
Test Conditions
Over T
OP
Over T
OP
Phase comparison frequency (F
OUT
鈭咶)
Reference breakthrough (F
OUT
鹵F
R
)
SSB at 1 kHz offset from carrier
SSB at 10 kHz offset from carrier
SSB at 100 kHz offset from carrier
SSB at 1.25 MHz offset from carrier
3
Units
MHz
dBm
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ms
mA
mA
Min.
1780
-3.0
鈥?
鈥?
鈥?
鈥?
鈥?
鈥?
鈥?
鈥?
鈥?
鈥?
+4.75
+4.75
鈥?
3
Typ.
鈥?
鈥?
-15
-80
-90
-70
-98
-118
-139
40
17
10
鈥?
鈥?
50
鈥?
Max.
1850
+3.0
-10
-60
鈥?
-65
-90
-110
鈥?
鈥?
20
15
+5.25
+5.25
鈥?
20
Frequency Switching Time
VCO Supply Current (I
CC1
)
PLL Supply Current (I
CC2
)
5,6
Over F
OUT
, measured to within 鹵500 Hz
VCO Supply Voltage (V
CC1
)
PLL Supply Voltage (V
CC2
)
Step Size (鈭咶)
7
8
Recommended operating limit
Recommended operating limit
Recommended operating limit
0.5 to 2.0 Vpp sine wave into a.c. coupled
CMOS. Recommended operating limit
V
V
kHz
MHz
Reference Frequency (F
R
)
1. All specification limits are indicated values and apply over F
OUT
and
for 50鈩?load impedance.
2. Programming control is 3 wire serial CMOS or TTL levels, in accor-
dance with National Semiconductor LMX 2325.
3. Output power window includes variation over operating temperature
range (T
OP
) -40擄C to +85擄C and output frequency range (F
OUT
).
4. See plot for typical phase noise at other frequency offsets.
5. See plot for typical full band switching time measured to within
other offsets from final frequency.
6. Integral PLL lock monitor output, TTL high locked, TTL low un-
locked.
7. Device designed for loop bandwidth of 250Hz.
8. Reference frequency input impedance 10 k鈩?min.
V2.00
M/A-COM Division of AMP Incorporated
s
North America: Tel. (800) 366-2266, Fax (800) 618-8883
s
Asia/Pacific: Tel.+85 2 2111 8088,
Fax +85 2 2111 8087
s
Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
www.macom.com
AMP and Connecting at a Higher Level are trademarks.
Specifications subject to change without notice.
14.6

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