1. All specification limits are indicated values and apply over F
鈩?/div>
load impedance.
2. Programming control is 3 wire serial CMOS or TTL levels, in accor-
dance with National Semiconductor LMX 1511.
3. Output power window includes variation over operating temperature
range (T
OP
) -40擄C to +85擄C and output frequency range (F
OUT
).
4. See plot for typical phase noise at other frequency offsets.
5. See plot for typical full band switching time measured to within
other offsets from final frequency.
6. Integral PLL lock monitor output, TTL high locked, TTL low un-
locked.
7. Device designed for loop bandwidth of 200 Hz.
8. Reference frequency input impedance 10 k鈩?min.
V2.00
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s
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s
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Specifications subject to change without notice.