鈥?/div>
Diode Protection on All Inputs
All Outputs Buffered
Straight鈥揻orward m鈥揃it By n鈥揃it Expansion
No Additional Logic Elements Needed for Expansion
Multiplies and Adds Simultaneously
Positive Logic Design
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low鈥揚(yáng)ower TTL Loads or One Low鈥揚(yáng)ower
Schottky TTL Load Over the Rated Temperature Range
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = 鈥?55擄 to 125擄C for all packages.
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
V
V
鈥?0.5 to + 18.0
鹵
10
500
鈥?65 to + 150
Vin, Vout
Iin, Iout
PD
Tstg
Input or Output Voltage (DC or Transient)
鈥?0.5 to VDD + 0.5
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high鈥搃mpedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package鈥?/div>
Storage Temperature
mA
mW
v
v
EQUATIONS
S = (X x Y) + K + M
Where:
x Means Arithmetic Times.
+ Means Arithmetic Plus.
S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0,
K = K1 K0, M = M1 M0 (Binary Numbers).
Example:
Given: X = 2(1), Y = 3(11)
K = 1(01), M = 2(10)
Then:
S = (2 x 3) + 1 + 2 = 9
S = (10 x 11) + 01 + 10 = 1001
_
C
TL
Lead Temperature (8鈥揝econd Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
鈥燭emperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic 鈥淟鈥?Packages: 鈥?12 mW/
_
C From 100
_
C To 125
_
C
PIN ASSIGNMENT
Y1
M0
M1
C0
M2
C1 (S3)
S2
VSS
REV 3
1/94
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
Y0
X0
X1
K0
S0
K1
S1
NOTE: C0 connected to M2 for this size
multiplier. See general expansion
diagram for other size multipliers.
漏
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14554B
1
MOTOROLA
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2
3
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