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MC14528 Datasheet

  • MC14528

  • ON Semiconductor [Dual Monostable Multivibrator]

  • ONSEMI

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MC14528B
Dual Monostable
Multivibrator
The MC14528B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an output pulse over a wide range of widths, the duration
of which is determined by the external timing components, C
X
and
R
X
.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP鈥?6
P SUFFIX
CASE 648
MC14528BCP
AWLYYWW
1
16
SOIC鈥?6
D SUFFIX
CASE 751B
14528B
AWLYWW
1
Unit
V
V
mA
mW
擄C
擄C
擄C
SOEIAJ鈥?6
F SUFFIX
CASE 966
1
鹵
10
500
鈥?55 to +125
鈥?65 to +150
260
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
16
MC14528B
AWLYWW
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Separate Reset Available
Diode Protection on All Inputs
Triggerable from Leading or Trailing Edge Pulse
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacement with the MC14538B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8鈥揝econd Soldering)
Value
鈥?0.5 to +18.0
鈥?0.5 to V
DD
+ 0.5
ORDERING INFORMATION
Device
MC14528BCP
MC14528BD
MC14528BDR2
MC14528BF
MC14528BFEL
Package
PDIP鈥?6
SOIC鈥?6
SOIC鈥?6
SOEIAJ鈥?6
SOEIAJ鈥?6
Shipping
2000/Box
48/Rail
2500/Tape & Reel
See Note 1.
See Note 1.
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high鈥搃mpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
v
v
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
漏
Semiconductor Components Industries, LLC, 2000
1
March, 2000 鈥?Rev. 3
Publication Order Number:
MC14528B/D

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