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MC145192 Datasheet

  • MC145192

  • Motorola, Inc [Evaluation Board Manual]

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145192/D
Low-Voltage 1.1 GHz
PLL Frequency Synthesizer
Includes On鈥揃oard 64/65 Prescaler
The MC145192 is a low鈥搗oltage single鈥損ackage synthesizer with serial
interface capable of direct usage up to 1.1 GHz. A special architecture makes
this PLL very easy to program because a byte鈥搊riented format is utilized. Due
to the patented BitGrabber
鈩?/div>
registers, no address/steering bits are required for
random access
of the three registers. Thus, tuning can be accomplished via a
3鈥揵yte serial transfer to the 24鈥揵it A register. The interface is both SPI and
MICROWIRE
鈩?/div>
compatible.
The device features a single鈥揺nded current source/sink phase detector A
output and a double鈥揺nded phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single鈥揺nded phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
The MC145192 phase/frequency detector B
蠁
R and
蠁
V outputs can be
powered from 2.7 to 5.5 V. This is optimized for 3.0 V systems. The
phase/frequency detector A PDout output must be powered from 4.5 to 5.5 V,
and is optimized for a 5 volt supply.
This part includes a differential RF input which may be operated in a
single鈥揺nded mode. Also featured are on鈥揵oard support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on鈥揵oard circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double鈥揵uffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
20
MC145192
F SUFFIX
SOG PACKAGE
CASE 751J
1
20
1
DT SUFFIX
TSSOP
CASE 948D
ORDERING INFORMATION
MC145192F
MC145192DT
SOG Package
TSSOP
PIN ASSIGNMENT
REFout
LD
蠁
R
蠁
V
VPD
PDout
GND
Rx
TEST 1
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
REFin
DATA IN
CLOCK
ENABLE
OUTPUT A
OUTPUT B
VDD
TEST 2
VCC
fin
Maximum Operating Frequency: 1100 MHz @ Vin = 200 mV p鈥損
fin 10
Operating Supply Current: 6 mA Nominal at 2.7 V
Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.0 V
Operating Supply Voltage Range of Phase Frequency Detector A
(VPD Pin) = 4.5 to 5.5 V
Operating Supply Voltage Range of Phase Detector B (VPD Pin) = 2.7 to 5.5 V
Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
Gain of Current Source/Sink Phase/Frequency Detector Controllable via Serial Port
Operating Temperature Range: 鈥?40擄 to 85擄C
R Counter Division Range: (1 and) 5 to 8191
N Counter Division Range: 5 to 4095
A Counter Division Range: 0 to 63
Dual鈥揗odulus Capability Provides Total Division up to 262,143
High鈥揝peed Serial Interface: 2 Megabits per Second
Output A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General鈥揚urpose Digital Outputs 鈥?Output A: Totem鈥揚ole (Push鈥揚ull) with Four Output Modes
Output B: Open鈥揇rain
Power鈥揝aving Standby Feature with Patented Orderly Recovery for Minimizing Lock Times,
Standby Current: 30
碌A(chǔ)
Evaluation Kit Available (Part Number MC145192EVK)
See Application Note AN1253/D for Low鈥揚ass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 3
1/98
TN98012200
漏
Motorola, Inc. 1998
MOTOROLA
MC145192
1

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