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MC14070 Datasheet

  • MC14070

  • Quad 2-input Exclusive OR (XOR) Gate

  • Motorola   Motorola

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
CMOS SSI
Quad Exclusive 鈥淥R鈥?and 鈥淣OR鈥?Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P鈥揷hannel and N鈥揷hannel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired.
鈥?/div>
Supply Voltage Range = 3.0 Vdc to 18 Vdc
鈥?/div>
All Outputs Buffered
鈥?/div>
Capable of Driving Two Low鈥揚ower TTL Loads or One Low鈥揚ower
Schottky TTL Load Over the Rated Temperature Range
鈥?/div>
Double Diode Protection on All Inputs
鈥?/div>
MC14070B 鈥?Replacement for CD4030B and CD4070B Types
鈥?/div>
MC14077B 鈥?Replacement for CD4077B Type
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
MC14070B
MC14077B
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
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Unit
V
V
鈥?0.5 to + 18.0
Vin, Vout
Iin, Iout
PD
Input or Output Voltage (DC or Transient)
鈥?0.5 to VDD + 0.5
鹵
10
500
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package鈥?/div>
Storage Temperature
mA
mW
Tstg
TL
鈥?65 to + 150
260
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = 鈥?55擄 to 125擄C for all packages.
_
C
_
C
Lead Temperature (8鈥揝econd Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
鈥燭emperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic 鈥淟鈥?Packages: 鈥?12 mW/
_
C From 100
_
C To 125
_
C
20 ns
VDD
IDD
Vin
*
CL
* Inverted output on MC14077B only.
Vin
90%
50%
10%
1/f
50% DUTY CYCLE
20 ns
VDD
VSS
MC14070B
QUAD Exclusive OR
Gate
1
3
2
5
4
6
8
10
9
12
11
13
MC14077B
QUAD Exclusive NOR
Gate
1
3
2
5
4
6
8
10
9
12
11
13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
20 ns
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
PULSE
GENERATOR
*
#
VSS
CL
20 ns
INPUT
tPHL
OUTPUT
90%
50%
10%
90%
50%
10%
tPLH
PIN ASSIGNMENT
VDD
VSS
VOH
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
IN 2D
IN 1D
OUTD
OUTC
IN 2C
IN 1C
tTHL
* Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
VOL
tTLH
Figure 2. Switching Time Test Circuit and Waveforms
REV 3
1/94
漏
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14070B MC14077B
1

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