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MC14040BF Datasheet

  • MC14040BF

  • ON Semiconductor [12-Bit Binary Counter]

  • 218.69KB

  • ONSEMI

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MC14040B
12-Bit Binary Counter
The MC14040B 12鈥搒tage binary counter is constructed with MOS
P鈥揷hannel and N鈥揷hannel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple鈥揷arry binary counter. The device
advances the count on the negative鈥揼oing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency鈥揹riving circuits.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP鈥?6
P SUFFIX
CASE 648
MC14040BCP
AWLYYWW
1
16
SOIC鈥?6
D SUFFIX
CASE 751B
1
14040B
AWLYWW
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range
鈥?/div>
Common Reset Line
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacement for CD4040B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8鈥揝econd Soldering)
Value
鈥?0.5 to +18.0
鈥?0.5 to V
DD
+ 0.5
鹵
10
500
鈥?55 to +125
鈥?65 to +150
260
Unit
V
V
TSSOP鈥?6
DT SUFFIX
CASE 948F
16
14
040B
ALYW
1
mA
mW
擄C
擄C
擄C
SOEIAJ鈥?6
F SUFFIX
CASE 966
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
16
MC14040B
AWLYWW
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high鈥搃mpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
Device
MC14040BCP
MC14040BD
MC14040BDR2
MC14040BDT
MC14040BF
MC14040BFEL
Package
PDIP鈥?6
SOIC鈥?6
SOIC鈥?6
TSSOP鈥?6
SOEIAJ鈥?6
SOEIAJ鈥?6
Shipping
2000/Box
2400/Box
2500/Tape & Reel
96/Rail
See Note 1.
See Note 1.
v
v
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
漏
Semiconductor Components Industries, LLC, 2000
1
March, 2000 鈥?Rev. 3
Publication Order Number:
MC14040B/D

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