MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14034B
8-Bit Universal Bus Register
The MC14034B is a bidirectional 8鈥揵it static parallel/serial, input/output
bus register. The device contains two sets of input/output lines which allows
the bidirectional transfer of data between two buses; the conversion of serial
data to parallel form, or the conversion of parallel data to serial form.
Additionally the serial data input allows data to be entered shift/right, while
shift/left can be accomplished by hard鈥搘iring each parallel output to the
previous parallel bit input.
Other useful applications for this device include pseudo鈥搑andom code
generation, sample and hold register, frequency and phase鈥揷omparator,
address or buffer register, and serial/parallel input/output conversions.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Bidirectional Parallel Data Input
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range.
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacement for CD4034B.
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
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脦
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脦
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Value
Unit
V
V
鈥?0.5 to + 18.0
Vin, Vout
lin, lout
PD
Input or Output Voltage (DC or Transient)
鈥?0.5 to VDD + 0.5
鹵
10
500
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package鈥?/div>
Storage Temperature
mA
mW
Tstg
TL
鈥?65 to + 150
260
TA = 鈥?55擄 to 125擄C for all packages.
PIN ASSIGNMENT
B8
B7
B6
B5
B4
B3
B2
B1
A ENABLE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
A8
A7
A6
A5
A4
A3
A2
A1
C
A/S
P/S
_
C
_
C
Lead Temperature (8鈥揝econd Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
鈥燭emperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic 鈥淟鈥?Packages: 鈥?12 mW/
_
C From 100
_
C To 125
_
C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
鈮?/div>
(Vin or Vout)
鈮?/div>
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
DS
A/B
VSS
REV 3
1/94
漏
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14034B
135
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