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MC14027 Datasheet

  • MC14027

  • Dual J-K Flip-Flop

  • Motorola   Motorola

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14025B (see Page 6-5)
MC14025UB (see Page 6-14)
MC14027B
Dual J-K Flip-Flop
The MC14027B dual J鈥揔 flip鈥揻lop has independent J, K, Clock (C), Set (S)
and Reset (R) inputs for each flip鈥揻lop. These devices may be used in
control, register, or toggle functions.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge鈥揅locked Flip鈥揊lop Design 鈥?/div>
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive鈥揼oing edge
of the clock pulse
鈥?/div>
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacement for CD4027B
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
脦脦脦
脦
脦
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脦
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脦
脦
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脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
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脦
脦
脦
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脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦
脦脦脦
脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
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脦
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脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
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脦脦脦脦脦脦脦脦
脦
脦
脦
脦
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脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦
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Value
Unit
V
V
鈥?0.5 to + 18.0
鹵
10
500
Vin, Vout
lin, lout
PD
TL
Input or Output Voltage (DC or Transient)
鈥?0.5 to VDD + 0.5
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package鈥?/div>
Storage Temperature
mA
mW
Tstg
鈥?65 to + 150
260
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = 鈥?55擄 to 125擄C for all packages.
_
C
_
C
BLOCK DIAGRAM
7
6
3
5
J
C
K
R
Q
2
S
Q
1
Lead Temperature (8鈥揝econd Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
鈥燭emperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic 鈥淟鈥?Packages: 鈥?12 mW/
_
C From 100
_
C To 125
_
C
TRUTH TABLE
Inputs
C鈥?/div>
J
1
X
0
X
1
X
X
X
X
X
X
X
K
X
0
X
1
1
X
X
X
X
S
0
0
0
0
0
0
1
0
1
R
0
0
0
0
0
0
0
1
1
Qn鈥?/div>
0
1
0
1
Qo
X
X
X
X
Outputs*
Qn+1
1
1
0
0
Qo
Qn
1
0
1
Qn+1
0
0
1
1
Qo
Qn
0
1
1
No
Change
4
9
10
13
11
12
VDD = PIN 16
VSS = PIN 8
J
C
K
R
Q
14
S
Q
15
X = Don鈥檛 Care
鈥?= Level Change
鈥?= Present State
* = Next State
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
鈮?/div>
(Vin or Vout)
鈮?/div>
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
漏
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14027B
107

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