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MC14020BCP Datasheet

  • MC14020BCP

  • ON Semiconductor [14−Bit Binary Counter]

  • ONSEMI

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MC14020B
14-Bit Binary Counter
The MC14020B 14鈥搒tage binary counter is constructed with MOS
P鈥揷hannel and N鈥揷hannel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripple鈥揷arry binary counter. The device
advances the count on the negative鈥揼oing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency鈥揹ividing circuits.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP鈥?6
P SUFFIX
CASE 648
MC14020BCP
AWLYYWW
1
16
SOIC鈥?6
D SUFFIX
CASE 751B
1
14020B
AWLYWW
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range
鈥?/div>
Buffered Outputs Available from stages 1 and 4 thru 14
鈥?/div>
Common Reset Line
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacement for CD4020B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note NO TAG)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note NO TAG)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8鈥揝econd Soldering)
Value
鈥?0.5 to +18.0
鈥?0.5 to V
DD
+ 0.5
鹵
10
500
鈥?55 to +125
鈥?65 to +150
260
Unit
V
V
mA
mW
擄C
擄C
擄C
16
SOEIAJ鈥?6
F SUFFIX
CASE 966
1
TSSOP鈥?6
DT SUFFIX
CASE 948F
16
14
020B
ALYW
1
MC14020B
AWLYWW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high鈥搃mpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
Device
MC14020BCP
MC14020BD
MC14020BDR2
MC14020BDT
MC14020BF
MC14020BFEL
Package
PDIP鈥?6
SOIC鈥?6
SOIC鈥?6
TSSOP鈥?6
SOEIAJ鈥?6
SOEIAJ鈥?6
Shipping
2000/Box
48/Rail
2500/Tape & Reel
96/Rail
See Note 1.
See Note 1.
v
v
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
漏
Semiconductor Components Industries, LLC, 2000
1
March, 2000 鈥?Rev. 3
Publication Order Number:
MC14020B/D

MC14020BCP PDF文件相關(guān)型號(hào)

MC14020BD

MC14020BCP 產(chǎn)品屬性

  • ON Semiconductor

  • 計(jì)數(shù)器移位寄存器

  • Binary

  • Up

  • 1

  • PDIP-16

  • 14020

  • CMOS

  • 1

  • 3900 ns, 1725 ns, 1200 ns

  • + 125 C

  • - 55 C

  • Tube

  • Counter/Divider

  • Through Hole

  • 12

  • 3 V to 18 V

  • 25

  • 18 V

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