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MC14015BF Datasheet

  • MC14015BF

  • ON Semiconductor [Dual 4-Bit Static Shift Register]

  • ONSEMI

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MC14015B
Dual 4-Bit Static
Shift Register
The MC14015B dual 4鈥揵it static shift register is constructed with
MOS P鈥揷hannel and N鈥揷hannel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4鈥搒tate serial鈥搃nput/parallel鈥搊utput registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master鈥搒lave flip鈥揻lops. Data is shifted
from one stage to the next during the positive鈥揼oing clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial鈥搕o鈥損arallel conversion where low power
dissipation and/or noise immunity is desired.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP鈥?6
P SUFFIX
CASE 648
MC14015BCP
AWLYYWW
1
16
SOIC鈥?6
D SUFFIX
CASE 751B
1
16
TSSOP鈥?6
DT SUFFIX
CASE 948F
1
14
015B
ALYW
14015B
AWLYWW
鈥?/div>
Diode Protection on All Inputs
鈥?/div>
Supply Voltage Range = 3.0 Vdc to 18 Vdc
鈥?/div>
Logic Edge鈥揅locked Flip鈥揊lop Design 鈥?/div>
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
鈥?/div>
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range.
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8鈥揝econd Soldering)
Value
鈥?0.5 to +18.0
鈥?0.5 to V
DD
+ 0.5
鹵
10
500
鈥?55 to +125
鈥?65 to +150
260
Unit
V
V
mA
mW
擄C
擄C
擄C
SOEIAJ鈥?6
F SUFFIX
CASE 966
16
MC14015B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
MC14015BCP
MC14015BD
MC14015BDR2
MC14015BDT
MC14015BF
MC14015BFEL
Package
PDIP鈥?6
SOIC鈥?6
SOIC鈥?6
Shipping
2000/Box
48/Rail
2500/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high鈥搃mpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
TSSOP鈥?6 2000/Tape & Reel
SOEIAJ鈥?6
SOEIAJ鈥?6
See Note 1.
See Note 1.
v
v
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
漏
Semiconductor Components Industries, LLC, 2000
1
March, 2000 鈥?Rev. 3
Publication Order Number:
MC14015B/D

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