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MC14007 Datasheet

  • MC14007

  • ON Semiconductor [Dual Complementary Pair Plus Inverter]

  • ONSEMI

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MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multi鈥損urpose device consists of three
N鈥揷hannel and three P鈥揷hannel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulse鈥搒hapers, linear amplifiers, high input
impedance amplifiers, threshold detectors, transmission gating, and
functional gating.
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP鈥?4
P SUFFIX
CASE 646
MC14007UBCP
AWLYYWW
1
14
SOIC鈥?4
D SUFFIX
CASE 751A
1
14007U
AWLYWW
鈥?/div>
Diode Protection on All Inputs
鈥?/div>
Supply Voltage Range = 3.0 Vdc to 18 Vdc
鈥?/div>
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacement for CD4007A or CD4007UB
鈥?/div>
This device has 2 outputs without ESD Protection. Anti鈥搒tatic
precautions must be taken.
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8鈥揝econd Soldering)
Value
鈥?0.5 to +18.0
鈥?0.5 to V
DD
+ 0.5
鹵
10
500
鈥?55 to +125
鈥?65 to +150
260
Unit
V
V
14
mA
mW
擄C
擄C
擄C
SOEIAJ鈥?4
F SUFFIX
CASE 965
1
TSSOP鈥?4
DT SUFFIX
CASE 948G
14
14
007U
ALYW
1
MC14007U
AWLYWW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high鈥搃mpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
Device
MC14007UBCP
MC14007UBD
MC14007UBDR2
MC14007UBDT
MC14007UBF
MC14007UBFEL
Package
PDIP鈥?4
SOIC鈥?4
SOIC鈥?4
TSSOP鈥?4
SOEIAJ鈥?4
SOEIAJ鈥?4
Shipping
2000/Box
55/Rail
2500/Tape & Reel
96/Rail
See Note 1.
See Note 1.
v
v
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
漏
Semiconductor Components Industries, LLC, 2000
1
March, 2000 鈥?Rev. 3
Publication Order Number:
MC14007UB/D

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