鈥?/div>
50 to 800MHz Differential PECL Outputs
鹵25ps
Typical Peak鈥搕o鈥揚(yáng)eak Output Jitter
Minimal Frequency Over鈥揝hoot
Synthesized Architecture
Serial 3鈥揥ire Interface
Parallel Interface for Power鈥揢p
Quartz Crystal Interface
28鈥揕ead PLCC Package
Operates from 3.3V or 5.0V Power Supply
FN SUFFIX
28鈥揕EAD PLCC PACKAGE
CASE 776鈥?2
Functional Description
The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference
oscillator is sent directly to the phase detector. With a 16.66MHz crystal, this provides a reference frequency of 16.66MHz.
Although this data sheet illustrates functionality only for a 16MHz and 16.66MHz crystal, any crystal in the 10鈥?0MHz range can
be used. In addition to the crystal, an LVCMOS input can also be used as the PLL reference. The reference is selected via the
XTAL_SEL input pin.
The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This
divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
in 50鈩?to VCC 鈥?2.0.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW鈥搕o鈥揌IGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH鈥搕o鈥揕OW edge of the S_LOAD input. See the
programming section for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the
PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de鈥揳ssertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
1/97
漏
Motorola, Inc. 1997
1
REV 3
1
2
3
4
5
6
7
8
9
10
11
