鈥?/div>
Pb鈭扚ree Packages are Available*
LOGIC DIAGRAM
E0 14
10 Q0 3
11 Q0 2
A9
12 Q0 1
V
CC1
= PIN 1
13 Q0 0 V
CC2
= PIN 16
V
EE
= PIN 8
3 Q1 3
4 Q1 2
5 Q1 1
6 Q1 0
20 1
PLLC鈭?0
FN SUFFIX
CASE 775
16
1
PDIP鈭?6
P SUFFIX
CASE 648
16
MC10H171P
AWLYYWWG
1
1 20
10H171G
AWLYYWW
B7
E 15
E1 2
DIP
PIN ASSIGNMENT
V
CC1
E1
Q13
Q12
Q11
Q10
B
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
E
E0
Q00
Q01
Q02
Q03
A
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Pin assignment is for Dual鈭抜n鈭扡ine Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
March, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
MC10H171/D
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