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MC10H161_06 Datasheet

  • MC10H161_06

  • ON Semiconductor [Binary to 1−8 Decoder (Low)]

  • ONSEMI

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MC10H161
Binary to 1鈭? Decoder
(Low)
Description
The MC10H161 provides parallel decoding of a three bit binary
word to one of eight lines. The MC10H161 is useful in high鈭抯peed
multiplexer/demultiplexer applications.
The MC10H161 is designed to decode a three bit input word to one
of eight output lines. The MC10H161 output will be low when
selected while all other output are high. The enable inputs, when either
or both are high, force all outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal
parallel path delay times found in other decoder designs. These
devices are ideally suited for multiplexer/demultiplexer applications.
Features
http://onsemi.com
MARKING DIAGRAMS*
16
MC10H161L
AWLYYWW
CDIP鈭?6
L SUFFIX
CASE 620A
1
鈥?/div>
Propagation Delay, 1.0 ns Typical
鈥?/div>
Power Dissipation, 315 mW Typical (same as MECL 10K鈩?
鈥?/div>
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
鈥?/div>
Voltage Compensated
鈥?/div>
MECL 10K Compatible
鈥?/div>
Pb鈭扚ree Packages are Available*
DIP PIN ASSIGNMENT
V
CC1
E0
Q3
Q2
Q1
Q0
A
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
E1
Pin assignment is for Dual鈭抜n鈭扡ine
C
Package. For PLCC pin assignment, see
Q4
the Pin Conversion Tables on page 18 of
Q5
16
16
1
PDIP鈭?6
P SUFFIX
CASE 648
1
MC10H161P
AWLYYWWG
10H161
ALYWG
Q6
Q7
B
the ON Semiconductor MECL Data
Book (DL122/D).
SOEIAJ鈭?6
CASE 966
1 20
LOGIC DIAGRAM
E0 2
E1 15
V
CC1
= Pin 1
V
CC2
= Pin 16
V
EE
= Pin 8
A 7
6 Q0
ENABLE
INPUTS
5 Q1
E1 E0
L
L
L
L
4 Q2
L
L
L
L
3 Q3
L
L
L
L
13 Q4
L
L
L
L
12 Q5
H X
X H
11 Q6
C 14
10 Q7
TRUTH TABLE
INPUTS
OUTPUTS
C B A Q0 Q1 Q2 Q3 Q4 Q5
L L L L H H H H H
L L H H L H H H H
L H L H H L H H H
L H H H H H L H H
H L L H H H H L H
H L H H H H H H L
H H L H H H H H H
H H H H H H H H H
X X X H H H H H H
X X X H H H H H H
20 1
PLLC鈭?0
FN SUFFIX
CASE 775
A
WL, L
YY, Y
WW, W
G
10H161G
AWLYYWW
B 9
Q6
H
H
H
H
H
H
L
H
H
H
Q7
H
H
H
H
H
H
H
L
H
H
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
February, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
MC10H161/D

MC10H161_06 PDF文件相關(guān)型號(hào)

MC10H161FNG,MC10H161FNR2,MC10H161FNR2G,MC10H161M,MC10H161MEL,MC10H161MG,MC10H161PG

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