鈥?/div>
Pb鈭扚ree Packages are Available*
3
4
5
6
7
9
10
11
12
13
14
15
16
16
1
PDIP鈭?6
P SUFFIX
CASE 648
1
MC10H160P
AWLYYWWG
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
2
TRUTH TABLE
INPUT
Sum of
High Level
Inputs
Even
Odd
OUTPUT
Pin 2
Low
High
10H160
ALYWG
SOEIAJ鈭?6
CASE 966
1 20
DIP
PIN ASSIGNMENT
V
CC1
OUT
IN1
IN2
IN3
IN4
IN5
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
IN12
IN11
IN10
IN9
IN8
IN7
IN6
20 1
PLLC鈭?0
FN SUFFIX
CASE 775
A
WL, L
YY, Y
WW, W
G
10H160G
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
Pin assignment is for Dual鈭抜n鈭扡ine Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
February, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC10H160/D
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