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MC10H135_06 Datasheet

  • MC10H135_06

  • ON Semiconductor [Dual J−K Master−Slave...

  • 154.02KB

  • ONSEMI

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MC10H135
Dual J鈭扠 Master鈭扴lave
Flip鈭扚lop
Description
The MC10H135 is a dual J鈭扠 master鈭抯lave flip鈭抐lop. The device is
provided with an asynchronous set(s) and reset(R). These set and reset
inputs overide the clock.
A common clock is provided with separate J鈭扠 inputs. When the
clock is static, the JK inputs do not effect the output. The output states
of the flip flop change on the positive transition of the clock.
Features
http://onsemi.com
MARKING DIAGRAMS*
16
MC10H135L
AWLYYWW
CDIP鈭?6
L SUFFIX
CASE 620A
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Propagation delay, 1.5 ns Typical
Power Dissipation, 280 mW Typical/Pkg. (No Load)
f
tog
250 MHz Max
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
鈥?/div>
Voltage Compensated
鈥?/div>
MECL 10K鈩?Compatible
鈥?/div>
Pb鈭扚ree Packages are Available*
16
16
1
PDIP鈭?6
P SUFFIX
CASE 648
1
MC10H135P
AWLYYWWG
10H135
ALYWG
SOEIAJ鈭?6
CASE 966
1 20
20 1
PLLC鈭?0
FN SUFFIX
CASE 775
A
WL, L
YY, Y
WW, W
G
10H135G
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
February, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC10H135/D

MC10H135_06 PDF文件相關(guān)型號(hào)

MC10H135FNG,MC10H135MG

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