MC10EL34, MC100EL34
5V ECL
梅2, 梅4, 梅8
Clock
Generation Chip
The MC10/100EL34 is a low skew
梅2, 梅4, 梅8
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V
BB
pin, an internally
generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
The 100 Series contains temperature compensation.
http://onsemi.com
MARKING
DIAGRAMS
16
SO鈥?6
D SUFFIX
CASE 751B
1
16
10EL34
AWLYWW
1
16
100EL34
AWLYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC10EL34D
MC10EL34DR2
MC100EL34D
MC100EL34DR2
Package
SO鈥?6
SO鈥?6
SO鈥?6
SO鈥?6
Shipping
48 Units / Rail
2500 Units / Reel
48 Units / Rail
2500 Units / Reel
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: > 1 KV HBM, > 100 V MM
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 鈥?.2 V to 鈥?.7 V
鈥?/div>
Internal Input Pulldown Resistors on CLK(s), EN, and MR
鈥?/div>
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
鈥?/div>
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
鈥?/div>
Flammability Rating: UL鈥?4 code V鈥? @ 1/8鈥?
Oxygen Index 28 to 34
鈥?/div>
Transistor Count = 191 devices
漏
Semiconductor Components Industries, LLC, 2000
1
October, 2000 鈥?Rev. 3
Publication Order Number:
MC10EL34/D
MC10EL34D 產(chǎn)品屬性
ON Semiconductor
時鐘發(fā)生器及支持產(chǎn)品
SMD/SMT
SOIC-16
Tube
48
1
2
3
4
5
6
7
8
