音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

MC100LVEP34_06 Datasheet

  • MC100LVEP34_06

  • ON Semiconductor [2.5V / 3.3V ECL ±2, ±4, ±8 Clock Gener...

  • ONSEMI

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

MC100LVEP34
2.5V / 3.3V ECL
梅2, 梅4, 梅8
Clock Generation Chip
The MC100LVEP34 is a low skew
梅2, 梅4, 梅8
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The V
BB
pin, an internally
generated voltage supply, is available to this device only. For
single鈭抏nded input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01
mF
capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip鈭抐lop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start鈭抲p, the internal flip鈭抐lops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEP34s in a system. Single鈭抏nded CLK
input operation is limited to a V
CC
鈮?/div>
3.0 V in PECL mode, or V
EE
鈮?/div>
鈭?.0
V in NECL mode.
Features
http://onsemi.com
MARKING
DIAGRAMS*
16
16
1
SO鈭?6
D SUFFIX
CASE 751B
1
100LVEP34G
AWLYWW
16
16
1
TSSOP鈭?6
DT SUFFIX
CASE 948F
A
L, WL
Y
W, WW
G or
G
100
VP34
ALYWG
G
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
35 ps Output鈭抰o鈭扥utput Skew
Synchronous Enable/Disable
Master Reset for Synchronization
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range: V
CC
= 2.375 V to 3.8 V
with V
EE
= 0 V
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.375
V to
鈭?.8
V
鈥?/div>
Open Input Default State
鈥?/div>
LVDS Input Compatible
鈥?/div>
Pb鈭扚ree Packages are Available
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 9
1
Publication Order Number:
MC100LVEP34/D

MC100LVEP34_06 PDF文件相關(guān)型號

MC100LVEP34DR2G

MC100LVEP34_06相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！