MC100LVEL38
3.3V ECL
梅2, 梅4/6
Clock
Generation Chip
Description
The MC100LVEL38 is a low skew
梅2, 梅4/6
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either a
differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as can happen with an
asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the
梅2
and the
梅4/6
outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the
梅2
and the
梅4/6
outputs of a
single device.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
http://onsemi.com
SO鈭?0 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL38
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
鈥?/div>
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
鈭?.0
V to
鈭?.8
V
鈥?/div>
Internal Input 75 kW Pulldown Resistors
鈥?/div>
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
鈥?/div>
Moisture Sensitivity Level 1
For Additional Information, see Application Note
AND8003/D
鈥?/div>
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
鈥?/div>
Transistor Count = 388 devices
鈥?/div>
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 8
1
Publication Order Number:
MC100LVEL38/D
MC100LVEL38_06 PDF文件相關(guān)型號
MC100LVEL38DWG,MC100LVEL38DWR2G
MC100LVEL38_06相關(guān)型號PDF文件下載
1
2
3
4
5
6
7
