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MC100LVEL29DWG Datasheet

  • MC100LVEL29DWG

  • ON Semiconductor [3.3V ECL Dual Differential Data and Clock...

  • ONSEMI

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MC100LVEL29
3.3V ECL Dual Differential
Data and Clock D Flip鈭扚lop
With Set and Reset
Description
The MC100LVEL29 is a dual master鈭抯lave flip flop. The device
features fully differential Data and Clock inputs as well as outputs.
The MC100LVEL29 is pin and functionally equivalent to the
MC100EL29. Data enters the master latch when the clock is LOW and
transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to V
EE
and the D input will
bias around V
CC
/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
http://onsemi.com
SO鈭?0 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL29
AWLYYWWG
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
鈥?/div>
鈥?/div>
Pb鈭扚ree Packages are Available*
1100 MHz Flip鈭扚lop Toggle Frequency
ESD Protection: >2 kV Human Body Model
580 ps Typical Propagation Delays
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.0
V to
鈭?.8
V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V鈭? @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 313 devices
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 5
1
Publication Order Number:
MC100LVEL29/D

MC100LVEL29DWG PDF文件相關(guān)型號(hào)

MC100LVEL29DWR2G

MC100LVEL29DWG 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 100LVEL

  • 設(shè)置（預(yù)設(shè)）和復(fù)位

  • D 型

  • 差分

  • 2

  • 1

  • 1.1GHz

  • 580ps

  • 正邊沿

  • -

  • 3 V ~ 3.8 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 管件

  • MC100LVEL29DWGOS

MC100LVEL29DWG相關(guān)型號(hào)PDF文件下載

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